Job Details

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists, in partnership with world-class sales, marketing, and support teams, developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, with a total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you thrive in a fast-paced, results-oriented environment, seek individual success within a "team first" organization, and believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may be just what you're looking for.

Responsibilities & Skills

We are seeking a passionate digital design engineer to build the High Speed Serial Protocol Hard-IP portfolio for Lattice FPGA. The candidate should work closely with Principal Engineers or Architects to translate specifications into RTL design, optimizing for performance, low power, and logic utilization.

Accountabilities/Exposure:

• Own unit-level design and IP integration.
• Perform design quality checks using industry-standard EDA tools and methodologies.
• Define design timing constraints and ensure timing convergence.
• Plan open-box testing, develop assertion checks, and debug.
• Conduct code coverage analysis and ensure closure.
• Support silicon power-on and post-silicon validation.
• Develop new design methodologies.
• Automate design flows through scripting for daily tasks.
• Create design documentation, including micro-architecture and implementation details.

Qualifications:

• Understanding of ASIC/FPGA IP or SoC development cycles.
• Knowledge of High-Speed Serial Protocols such as Ethernet, PCIe, MIPI, or Universal Transceivers.
• Proficiency in RTL design using Verilog or SystemVerilog and design constraints.
• Experience with design quality check methodologies like Lint, CDC, RDC, Fishtail, or UPF flows.
• Advanced skills with logic simulation EDA tools such as Cadence Xcelium, Synopsys VCS, or Siemens Questa.
• Experience collaborating with Design Verification teams on test planning, assertions, coverage analysis, and debugging.
• Familiarity with Physical Design processes like Synthesis, LEC, or Timing Closure.
• Programming skills in Perl, Shell Scripting, TCL, Java, Python, or C/C++, and familiarity with Linux OS.
• Experience in technical writing, including micro-architecture documentation, publications, or patents.
• Self-motivated with strong communication skills, promoting innovation and teamwork.
• Experience with silicon power-on or hardware validation is a plus.
• Experience in team supervision or leading design delivery is a plus.